1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to forming long-channel gates, with or without grooves, in high-density Dynamic Random Access Memories (DRAM).
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in Dynamic Random Access Memory (DRAM) technologies, as more computers and peripherals come with higher amounts of DRAM in order to run the memory-intensive applications being developed. In addition, smaller sizes for DRAMs allow the semiconductor manufacturer to produce more DRAM chips with each silicon wafer, which increases productivity and profit.
A typical DRAM chip is made of millions of individual DRAM xe2x80x9ccells.xe2x80x9d Each cell contains a capacitor used to store the memory charge, a switch used to access the capacitor, and some isolation regions around these devices. The individual cells are accessed using a large number of bit lines and word lines. By selecting an appropriate bit line and word line, a memory controller can write or read information into or from, respectively, the desired DRAM cells.
The density of a DRAM chip is determined in large part by the area needed for each DRAM cell. This area is often measured in terms of xe2x80x9csquares,xe2x80x9d where a square comprises a 1 Fxc3x971 F square region where xe2x80x9cFxe2x80x9d is the minimum feature dimension that can be created using an aerial image in a given lithography system. Thus, an 8 SQ DRAM cell created by a 0.35 xcexcm lithography system comprises an area of eight 0.35 xcexcm by 0.35 xcexcm squares on the chip. It is desirable to have the smallest area for each DRAM cell so that more cells can be packed into a smaller area.
Problems can arise with decreasing DRAM cell size, however. One important and potentially very serious problem is the associated decrease in capacitance that generally follows a decrease in cell size. It is desirable that each cell have a high capacitance because the capacitor stores the charge that will be subsequently read by the memory controller. All capacitors lose charge over time. Because of this, DRAM chips include circuitry that will periodically read and then refresh each and every cell in the chip. But it takes some time for the refresh circuitry to access and refresh each cell in the array, particularly when more cells are placed into an array. Each cell must maintain its charge until refreshed, and this time period could be quite long, particularly with DRAMs"" increasing cell numbers and density.
In addition to lower capacitance, as cell sizes decrease, sub-threshold leakage tends to increase. Many of the causes of leakage actually decrease as cells and gate sizes decrease, but one important cause of leakage increases. This is drain induced barrier lowering, which occurs when the drain is charged to a high voltage and the source is a low voltage. In this leakage, the source essentially xe2x80x9cstealsxe2x80x9d electric field from the drain. This causes the entire barrier between the drain and the source to be lowered. Drain induced barrier lowering becomes the predominant cause of leakage as cell and gate size decrease. This current leakage reduces the time that the capacitor will store a charge and can cause potential errors if charge from the capacitor is transferred to the bit line or vice versa.
Thus, the length of the gates in DRAM cells is important for controlling leakage current from and into the capacitors. The greater the leakage current, the quicker the cells must be refreshed. Unfortunately, with increasing density of cells on a chip, the refresh circuitry will take longer to refresh each cell. In addition, the increased density of cells comes by making each cell smaller. This causes each gate length, and the corresponding channel length under the gate, to also become small, which leads to increased sub-threshold leakage from DRAM capacitors.
Therefore, without a way to increase the length of the gates without increasing the size of cells, increasing density of cells in DRAMs will cause greater leakage current or errors and more complex and costly refresh circuitry to counteract the increased leakage.
Accordingly, the present invention lengthens gate conductors used in memory devices to limit leakage current, while still allowing the overall size of cells to remain the same. The channel length for each gate is increased by decreasing the size of spaces between gates. Decreases in space size occurs by using photolithographic image enhancement techniques. These techniques allow the space between gate conductors to be smaller while the gate size increases. In addition, a groove may be added that additionally lengthens the effective channel length and provides an additional electrical shield to limit leakage current. These techniques lead to the same density memory cells for a given process with less leakage. Finally, if grooved gate structures are used, having a longer gate conductor allows a three sigma process to be used, which increases yields.
The foregoing and other advantages and features of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.